1. Field of the Invention
Embodiments of the invention relate to methods for polishing regions of semiconductor wafers. In particular embodiments, the invention relates to methods of polishing a wafer to form isolation structures.
2. Background of the Invention
During the manufacture of semiconductor devices, a wafer undergoes a sequence of photolithography-etching steps to produce a plurality of patterned layers. In order to avoid adjacent devices from shorting to one another, and in order to avoid leakage between devices formed in close proximity to one another, shallow trench isolation (STI) structures have become a commonly used feature in the semiconductor manufacturing industry.
The process for forming an STI structure typically involves forming a trench-like opening in a silicon substrate, then filling the trench opening with an insulating material. The insulating materials may be formed by deposition techniques such as low pressure chemical vapor deposition (LPCVD), high density plasma (HDP) deposition, or any other suitable method for depositing an insulating material within a trench opening. After the opening is filled with a deposited insulating material, a polishing process is used to planarize the surface by removing any portions of the insulating material which may be formed above the upper plane beneath which the trench opening extends.
A nitride, such as silicon nitride, or other oxidation resistant, and suitably hard films, are typically used as hard masks for trench-formation silicon etches and also as polishing stop layers for CMP operations. In this manner, the nitride or other, hard, oxidation-resistant film forms the upper surface beneath which the trench opening extends. Hard films have relatively low removal rates and may be referred to as polishing stop layers.
During the formation of STI structures, problems arise when the polishing operations used to polish the insulating material and planarize the STI structure, cause “dishing” on the top of the STI structure. Dishing describes the phenomena wherein the top surface of the insulating material within the trench, becomes recessed below the upper surface of the polishing stop layer such as silicon nitride. Typically, the central portion of the top surface of the STI structure is recessed below the peripheral portion of the top surface of the STI structure. The peripheral edges of the STI structure generally extend up the side of the trench opening to intersect the upper surface of the polishing stop layer at the edges of the trench opening. Sharp, upward projections of the insulating material may therefore result at these peripheral edges.
After the STI structure is completed, the sharp, upward projections may remain at the edges of the STI structure which may additionally extend above the upper surface of the semiconductor substrate by as much as 500 Å, and may extend above the surrounding semiconductor substrate by an even greater distance. These sharp upward projections in the STI structure created by dishing can cause other electrical problems which may result in device failure, or which may require additional implants to compensate for changed parametric characteristics, or both.